Communications systems often employ digital signal processors (DSPs) on the receiver end of a communications channel. The DSPs apply amplification, filtering and/or equalization to reduce attenuation, distortion and other channel effects. The channel may cause intersymbol interference (ISI), for example when the transmitted signals have a data rate that exceeds the bandwidth of the communications channel. When a transmitted symbol having a period of T is transmitted, the received signal may have a period that exceeds T, which may interfere with subsequent transmitted symbols.
Referring now to FIG. 1, an exemplary digital signal processor (DSP) 30 receives a signal from a communications channel. The transmitted signal may be a differential signal {1, −1} or any other type of signal. The DSP 30 includes an analog portion 32 and a digital portion 34. The analog portion 32 includes an amplifier 40 that receives the analog input signal from the communications channel. An output of the amplifier 40 is input to an analog to digital converter (ADC) 42, which converts the received analog signal to a digital signal.
An output of the ADC 42 is input to a finite impulse response (FIR) filter 44, which performs filtering using one or more taps and delay elements. An output of the FIR filter 44 is input to a non-inverting input of a summer 48, which has an output that is input to a decision circuit 50 and to a non-inverting input of a summer 54. The decision circuit 50 attempts to identify the transmitted signal based upon the received signal. The decision circuit 50 is typically implemented using a comparator, which compares the received signal to a predetermined threshold.
An output of the decision circuit 50 is input to an inverting input of the summer 54 and to an input of a decision feedback equalizer (DFE) 58. The DFE 58 is operated in a manner that is similar to a FIR filter. The DFE 58 attempts to eliminate the ISI effects of a detected symbol on future received symbols. The DFE 58 includes one or more taps having tap weights and one or more delay elements. An output of the DFE 58 is fed back to an inverting input of the summer 48.
An output of the summer 54 is input to an adaptation circuit 60, which gradually adjusts parameters of the DSP 30 to minimize errors. For example, the adaptation circuit 60 may be a least means squared (LMS) adaptation circuit. The adaptation circuit 60 outputs adjusted tap weights to the DFE 58 and adjusted timing to a phase locked loop (PLL) 64. The adaptation circuit 60 may also output an automatic gain control (AGC) signal to the amplifier 40, which adjusts the gain of the amplifier 40. The PLL 64 receives the timing adjustments and outputs a clock signal to the ADC 42.
Referring now to FIGS. 2 and 3, the DFE 58 is shown in further detail. In FIG. 2, the received signal x from the communications channel is input to the summer 48, which has an output y that is input to the decision circuit 50. An output of the decision circuit 50 or ŷ is input to a multiplier 84, which has another input that is connected to a tap weight w0. The output of the decision circuit 50 is also input to a delay element 86. An output of the delay element 86 is input to a multiplier 88, which has another input that is connected to a tap weight w1. The output of the delay element is also input to a delay element 90. An output of the delay element 90 is input to a multiplier 92, which has another input that is connected to a tap weight w2. Outputs of the multipliers 84, 88 and 92 are input to the summer 48. As can be appreciated, additional or fewer delay elements and tap weights can be used.
In the example illustrated in FIG. 2, the DFE 58 implements the function:
            y      k        =                  x        k            -              (                                                            y                ^                            k                        ⁢                          w              0                                +                                                    y                ^                                            k                -                1                                      ⁢                          w              1                                +                                                    y                ^                                            k                -                2                                      ⁢                          w              2                                      )                        y      k        =                  x        k            -                        ∑                      i            =            0                    N                ⁢                                  ⁢                                            y              ^                                      k              -              i                                ⁢                      w            i                              The tap weight w0 of the DFE 58 defines a critical path that is shown in a simplified form in FIG. 3. When the transmitted signal {circumflex over (x)} is transmitted over a communications channel, the transmitted signal {circumflex over (x)} is altered by the communications channel. The function H(s) in FIG. 3 represents the transfer function of the communications channel. The transmitted signal {circumflex over (x)}={1, −1} is the desired signal and x is the received signal after transmission over the channel, where x={circumflex over (x)}*H(s) and where * is a convolution function.
The critical path 96 is formed by a path y→decision block→ŷ→ŷw0→x−ŷw0=1T. As the frequency of operation increases and approaches and/or exceeds 1 GHz, the ADC 42 becomes increasingly more difficult to implement. Even if the ADC 42 can be implemented at a desired high operating frequency, the power that is required to operate the ADC 42 becomes prohibitive.